1. Field of the Invention
The present invention relates to an internal power-source potential supply circuit for supplying an internal power-source potential to a predetermined load.
2. Description of the Background Art
FIG. 98 is a circuit diagram of a conventional internal power-source potential supply circuit for use in a semiconductor device. As shown, an external power-source potential VCE is applied as an internal power-source potential VCI to a load 11 through a PMOS transistor Q1. A comparator 1 has a negative input receiving a reference potential Vref and a positive input receiving the internal power-source potential VCI as a feedback signal, and provides a control signal S1 based on the result of comparison between the reference potential Vref and the internal power-source potential VCI to the gate of the PMOS transistor Q1.
In such an arrangement, if the internal power-source potential VCI is lower than the reference potential Vref, the control signal S1 from the comparator 1 has a lower potential to cause the PMOS transistor Q1 to conduct heavily. This increases the current supply capability from the external power-source potential VCE. Then, the circuit acts to raise the lowered internal power-source potential VCI. Conversely, if the internal power-source potential VCI is higher than the reference potential Vref, the control signal S1 from the comparator 1 has a higher potential to cause the PMOS transistor Q1 to conduct lightly. This stops the current supply capability from the external power-source potential VCE. Then, the circuit prevents further increase in raised internal power-source potential VCI. The comparator 1 may include a differential amplifier having a current mirror circuit or the like. In this manner, the internal power-source potential supply circuit may supply the internal power-source potential VCI equal to the reference potential Vref.
FIG. 99 is a circuit diagram of another conventional internal power-source potential supply circuit for use in a semiconductor device. As shown, the external power-source potential VCE is applied as the internal power-source potential VCI to the load 11 through the PMOS transistor Q1. The comparator 1 has a negative input receiving the reference potential Vref and a positive input receiving a divided internal power-source potential DVCI as a feedback signal.
The drain of the PMOS transistor Q1 is grounded through a resistor R11 and a resistor R12. The internal power-source potential VCI divided by the resistors R11 and R12 is applied as the divided internal power-source potential DVCI to the positive input of the comparator 1.
The circuit of FIG. 99 is advantageous in that the operating point of the comparator 1 may be freely selected, allowing the characteristics of the comparator 1 to be held satisfactory independently of the conditions set for the internal power-source potential VCI and external power-source potential VCE. In the arrangement of FIG. 98, a small difference between the external power-source potential VCE and the internal power-source potential VCI deteriorates the characteristics of the comparator 1, resulting in a delay in operation and a large amount of temporary reduction in internal power-source potential VCI.
The arrangement of FIG. 99 may supply the internal power-source potential VCI in a stable manner when the reference potential Vref is constant.
FIG. 100 is a graph indicating a drawback of the circuit of FIG. 99. In FIG. 100, (R11+R12)/R12=3/2. As shown in FIG. 100, a time interval T11 is defined during which the reference potential Vref rises to follow the varying external power-source potential VCE. During the time interval T11, the internal power-source potential VCI also rises to follow the varying external power-source potential VCE, but has a tendency to provide access to the external power-source potential VCE as the external power-source potential VCE increases. The internal power-source potential VCI grows higher than required, resulting in dangers of an increase in current consumption and a lower degree of reliability.
Additionally, the resistors R11 and R12 have fixed resistances, resulting in the fixed internal power-source potential VCI.
In this manner, the conventional internal power-source potential supply circuits are disadvantageous in that variations in the external power-source potential may cause decreased performance of the circuit, finding difficulties in supplying the internal power-source potential with high accuracy.